1. Field of the Invention
The present invention relates to a method of fabricating a memory device. More particularly, the present invention relates to a method for fabricating a flash memory.
2. Description of the Related Art
Conventional flash memory is a type of erasable programmable read-only memory (EPROM). There have been many articles written about flash memories. In general, the gate of a flash memory includes a polysilicon floating gate, which is used for storing electric charges, and a control gate, which is used for controlling data access. Therefore, EPROM normally has two gate terminals with the floating gate located below the control gate. The control gate and the word line are usually connected, and the floating gate is usually in a "floating" state. In other words, the floating gate is not in contact with any other circuits. An outstanding property of flash memory is its ability to perform a fast, block-by-block memory erase instead of the slow, bit-by-bit memory erase as in conventional EPROM. Consequently, operation speed of a flash memory is very fast. Often, the entire memory can be erased within one or two seconds.
FIGS. 1A through 1C are schematic, top view diagrams used to depict steps in a conventional method for fabricating a flash memory. FIGS. 2A through 2C are schematic, cross-sectional views of FIGS. 1A through 1C along a line II--II.
Referring to FIGS. 1A and 2A, a shallow trench isolation structure 102 is formed in a provided substrate 100 to define an active region 104.
Referring to FIGS. 1B and 2B, a tunneling oxide layer 106 and a patterned gate conductive layer 108 are formed in sequence on the active region 104.
Referring to FIGS. 1C and 2C, a silicon-oxy-nitride layer 110 and a polysilicon layer 112 are formed in sequence on the gate conductive layer 108 by chemical vapor deposition. The polysilicon layer 112, the silicon-oxy-nitride layer 110 and the gate conductive layer 108 are patterned to form a gate 114, wherein the polysilicon layer 112 is a control gate and the conductive layer 108 is a floating gate. An ion implantation process is performed to form a source/drain region 116, 118 in the substrate 100.
FIG. 3 is a schematic, top view of FIG. 1C.
Referring to FIG. 3, the shallow trench isolation structure 102 and the active region 104 are formed before forming the gate conductive layer 108. Thus, a misalignment problem occurs while forming the gate conductive layer 108. In general, the width 124 of the gate conductive layer 108 is formed larger than the one of the active region 104, so that the edge of the conductive layer 108 overlaps with the shallow trench isolation structure 102 (denoted by the reference numeral 120). The misalignment problem is avoided, however it is difficult to increase the integration of the devices.
Similarly, the misalignment problem also occurs while forming the polysilicon layer 112. The area overlapped by the active region 104 and the conductive layer 108 is changed because of the misalignment problem (denoted by the reference numeral 122). Thus, the coupling ratio of the adjacent memory cells is different. An odd-even effect occurs.
In order to increase the integration of the devices, the distance 128 between the shallow trench isolation structures 102 must be shorter. However, the source/drain region 116 is smaller when the distance 128 between the shallow trench isolation structures 102 is shorter. Thus, the resistance of the source/drain region 116 is increased. Also, the distance 126 between the polysilicon layers 112 is limited by the distance 128 between the shallow trench isolation structures 102, and it is difficult to increase the integration of the devices.